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IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
256K x 32, 256K x 36, 512K x 18 SYNCHRONOUS PIPELINE, DOUBLE-CYCLE DESELECT STATIC RAM
FEATURES
* Internal self-timed write cycle * Individual Byte Write Control and Global Write * Clock controlled, registered address, data and control * PentiumTM or linear burst sequence control using MODE input * Three chip enable option for simple depth expansion and address pipelining * Common data inputs and data outputs * JEDEC 100-Pin TQFP and 119-pin PBGA package * Single +3.3V, +10%, -5% power supply * Power-down snooze mode * 3.3V I/O For SPD * 2.5V I/O For LPD * Double cycle deselect * Snooze MODE for reduced-power standby * T version (three chip selects) * D version (two chip selects)
ISSI
(R)
PRELIMINARY INFORMATION SEPTEMBER 2000
DESCRIPTION The ISSI IS61SPD25632, IS61SPD25636, S61SPD51218,
IS61LPD25632, IS61LPD25636, and IS61LPD51218 are high-speed, low-power synchronous static RAMs designed to provide a burstable, high-performance, secondary cache for the PentiumTM, 680X0TM, and PowerPCTM microprocessors. The IS61SPD25632 and IS61LPD25632 are organized as 262,144 words by 32 bits and the IS61SPD25636 and IS61LPD25636 are organized as 262,144 words by 36 bits. The IS61SPD51218 and IS61LPS51218 are organized as 524,288 words by 18 bits. Fabricated with ISSI's advanced CMOS technology, the device integrates a 2-bit burst counter, high-speed SRAM core, and high-drive capability outputs into a single monolithic circuit. All synchronous inputs pass through registers controlled by a positive-edge-triggered single clock input. Write cycles are internally self-timed and are initiated by the rising edge of the clock input. Write cycles can be from one to four bytes wide as controlled by the write control inputs. Separate byte enables allow individual bytes to be written. Byte write operation is performed by using byte write enable (BWE).input combined with one or more individual byte write signals (BWx). In addition, Global Write (GW) is available for writing all bytes at one time, regardless of the byte write controls. Bursts can be initiated with either ADSP (Address Status Processor) or ADSC (Address Status Cache Controller) input pins. Subsequent burst addresses can be generated internally and controlled by the ADV (burst address advance) input pin. The mode pin is used to select the burst sequence order, Linear burst is achieved when this pin is tied LOW. Interleave burst is achieved when this pin is tied HIGH or left floating.
FAST ACCESS TIME
Symbol tKQ tKC Parameter Clock Access Time Cycle Time Frequency -166* 3.5 6 166 -150 3.8 6.7 150 -133 4 7.5 133 -5 5 10 100 Units ns ns MHz
*This speed available only in SPD version
This document contains PRELIMINARY INFORMATION data. ISSI reserves the right to make changes to its products at any time without notice in order to improve design and supply the best possible product. We assume no responsibility for any errors which may appear in this publication. (c) Copyright 2001, Integrated Silicon Solution, Inc.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
1
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
BLOCK DIAGRAM
MODE Q0 A0'
ISSI
A1'
(R)
CLK
CLK
A0
BINARY COUNTER
ADV ADSC ADSP A18-A0 (61SPD51218, 61LPD51218) A17-A0 (61SPD25632/36, 61LPD25632/36) CE CLR Q1 A1
256Kx32; 256Kx36; 512Kx18 MEMORY ARRAY
16/17 18/19 Q
18/19 D
ADDRESS REGISTER
CE CLK 32, 36, or 18 32, 36, or 18
GW BWE BWd (x32/x36)
DQd BYTE WRITE REGISTERS
CLK
D
Q
BWc (x32/x36)
D DQc Q BYTE WRITE REGISTERS CLK
BWb (x32/x36/x18)
DQb BYTE WRITE REGISTERS
CLK
D
Q
BWa (x32/x36/x18)
D DQa Q BYTE WRITE REGISTERS CLK
(T, D) CE (T, D) CE2 (T) CE2 D Q
4
ENABLE REGISTER
CE CLK
INPUT REGISTERS
CLK
OUTPUT REGISTERS
CLK OE
32, 36, or 18 DQa - DQd
D
Q
ENABLE DELAY REGISTER
CLK
OE
2
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View)
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ NC A10 A11 A14 NC ZZ A5 MODE VCC NC A13 NC NC GND A0 GND NC DQa1 DQd7 GND A1 GND DQa3 DQa2 DQd5 GND DQd3 DQd2 GND BWd CLK NC BWE GND BWa GND DQa7 DQa5 DQa4 DQa8 DQa6 VCCQ VCC NC VCC NC VCC VCCQ DQc8 GND DQc6 DQc4 GND BWc DQc3 GND NC GND NC CE OE ADV GW GND GND GND BWb GND NC DQb6 DQb5 DQb4 DQb2 DQb8 DQb7 VCCQ DQb3 DQb1 A7 A2 VCC A12 A15 NC CE2 A3 A6 A4 2 3 4 5 6 7
ISSI
100-Pin TQFP (D Version)
A6 A7 CE CE2 BWd BWc BWb BWa A17 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
(R)
ADSP ADSC
A8 A9
A16 A17
VCCQ NC
NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GNDQ GW CE, CE2 OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Isolated Output Buffer Ground
A2-A17 CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
3
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
A6 A7 CE CE2 BWd BWc BWb BWa CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
ISSI
(R)
NC DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC A17 A10 A11 A12 A13 A14 A15 A16
NC DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 NC
256K x 32
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ GNDQ GW OE DQa-DQd MODE VCC GND VCCQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Isolated Output Buffer Ground
CE, CE2, CE2 Synchronous Chip Enable
A2-A17 CLK ADSP ADSC ADV BWa-BWd BWE
4
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View)
1 A VCCQ B NC C NC D DQc1 E DQc2 F VCCQ G DQc5 H DQc7 J VCCQ K DQd1 L DQd4 M VCCQ N DQd6 P DQd8 R NC T NC U VCCQ NC NC NC NC NC VCCQ NC A10 A11 A14 NC ZZ A5 MODE VCC NC A13 NC DQPd GND A0 GND DQPa DQa1 DQd7 GND A1 GND DQa3 DQa2 DQd5 GND DQd3 DQd2 GND BWd CLK NC BWE GND BWa GND DQa7 DQa5 DQa4 DQa8 DQa6 VCCQ VCC NC VCC NC VCC VCCQ DQc8 GND DQc6 DQc4 GND BWc DQc3 GND DQPc GND NC CE OE ADV GW GND GND GND BWb GND DQPb DQb6 DQb5 DQb4 DQb2 DQb8 DQb7 VCCQ DQb3 DQb1 A7 A2 VCC A12 A15 NC CE2 A3 A6 A4 2 3 4 5 6 7
ISSI
100-Pin TQFP (D Version)
A6 A7 CE CE2 BWd BWc BWb BWa A17 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
(R)
ADSP ADSC
A8 A9
A16 A17
VCCQ NC
DQPc
DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2 OE DQa-DQd MODE VCC GND VCCQ ZZ DQPa-DQPd Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O
A2-A17 CLK ADSP ADSC ADV BWa-BWd BWE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
5
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
A6 A7 CE CE2 BWd BWc BWb BWa CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
ISSI
(R)
DQPc
DQc1 DQc2 VCCQ GND DQc3 DQc4 DQc5 DQc6 GND VCCQ DQc7 DQc8 NC VCC NC GND DQd1 DQd2 VCCQ GND DQd3 DQd4 DQd5 DQd6 GND VCCQ DQd7 DQd8 DQPd
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC A17 A10 A11 A12 A13 A14 A15 A16
DQPb DQb8 DQb7 VCCQ GND DQb6 DQb5 DQb4 DQb3 GND VCCQ DQb2 DQb1 GND NC VCC ZZ DQa8 DQa7 VCCQ GND DQa6 DQa5 DQa4 DQa3 GND VCCQ DQa2 DQa1 DQPa
256K x 36
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Individual Byte Write Enable Synchronous Byte Write Enable GW CE, CE2, CE2 OE DQa-DQd MODE VCC GND VCCQ ZZ DQPa-DQPd Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O
A2-A17 CLK ADSP ADSC ADV BWa-BWd BWE
6
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
119-pin PBGA (Top View)
1 A VCCQ B NC C NC D DQb1 E NC F VCCQ G NC H DQb4 J VCCQ K NC L DQb6 M VCCQ N DQb8 P NC R NC T NC U VCCQ NC NC NC NC NC VCCQ A11 A10 NC A14 A17 ZZ A5 MODE VCC NC A13 NC DQPb GND A0 GND NC DQa1 NC GND A1 GND DQa2 NC DQb7 GND NC GND NC BWE BWa GND DQa3 NC NC VCCQ DQb5 GND CLK GND NC DQa4 VCC NC VCC NC VCC VCCQ NC GND DQb3 BWb NC GND DQb2 GND NC GND NC CE OE ADV GW GND GND GND GND GND DQPa NC DQa7 NC DQa5 NC DQa8 VCCQ DQa6 NC A7 A2 VCC A12 A15 NC CE2 A3 A6 A4 2 3 4 5 6 7
ISSI
100-Pin TQFP (D Version)
A6 A7 CE CE2 NC NC BWb BWa A18 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
(R)
ADSP ADSC
A8 A9
A16 A18
VCCQ NC
NC NC NC VCCQ GND NC NC DQb1 DQb2 GND VCCQ DQb3 DQb4 VCC VCC NC GND DQb5 DQb6 VCCQ GND DQb7 DQb8 DQPb NC GND VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A17 NC NC VCCQ GND NC DQPa DQa8 DQa7 GND VCCQ DQa6 DQa5 GND NC VCC ZZ DQa4 DQa3 VCCQ GND DQa2 DQa1 NC NC GND VCCQ NC NC NC
512K x 18
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ DQPa-DQPb GW CE, CE2 OE DQa-DQb MODE VCC GND VCCQ Synchronous Global Write Enable Synchronous Chip Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O DQPa is parity for DQa1-8; DQPb is parity for DQb1-8
A2-A18 CLK ADSP ADSC ADV BWa-BWb BWE
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC NC A10 A11 A12 A13 A14 A15 A16
7
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
PIN CONFIGURATION
100-Pin TQFP (T Version)
A6 A7 CE CE2 NC NC BWb BWa CE2 VCC GND CLK GW BWE OE ADSC ADSP ADV A8 A9
ISSI
(R)
NC NC NC VCCQ GND NC NC DQb1 DQb2 GND VCCQ DQb3 DQb4 VCC VCC NC GND DQb5 DQb6 VCCQ GND DQb7 DQb8 DQPb NC GND VCCQ NC NC NC
100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 1 79 2 78 3 77 4 76 5 75 6 74 7 73 8 72 9 71 10 70 11 69 12 68 13 67 14 66 15 65 16 64 17 63 18 62 19 61 20 60 21 59 22 58 23 57 24 56 25 55 26 54 27 53 28 52 29 51 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50
A17 NC NC VCCQ GND NC DQPa DQa8 DQa7 GND VCCQ DQa6 DQa5 GND NC VCC ZZ DQa4 DQa3 VCCQ GND DQa2 DQa1 NC NC GND VCCQ NC NC NC
PIN DESCRIPTIONS
A0, A1 Synchronous Address Inputs. These pins must tied to the two LSBs of the address bus. Synchronous Address Inputs Synchronous Clock Synchronous Processor Address Status Synchronous Controller Address Status Synchronous Burst Address Advance Synchronous Byte Write Enable Synchronous Byte Write Enable ZZ DQPa-DQPb GW OE DQa-DQb MODE VCC GND VCCQ Synchronous Global Write Enable Output Enable Synchronous Data Input/Output Burst Sequence Mode Selection +3.3V Power Supply Ground Isolated Output Buffer Supply: +3.3V or 2.5V Snooze Enable Parity Data I/O DQPa is parity for DQa1-8; DQPb is parity for DQb1-8 CE, CE2, CE2 Synchronous Chip Enable
A2-A18 CLK ADSP ADSC ADV BWa-BWb BWE
8
MODE A5 A4 A3 A2 A1 A0 NC NC GND VCC NC A18 A10 A11 A12 A13 A14 A15 A16
512K x 18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
TRUTH TABLE
Operation Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Deselected, Power-down Read Cycle, Begin Burst Read Cycle, Begin Burst Write Cycle, Begin Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Read Cycle, Continue Burst Write Cycle, Continue Burst Write Cycle, Continue Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Read Cycle, Suspend Burst Write Cycle, Suspend Burst Write Cycle, Suspend Burst Address Used None None None None None External External External Next Next Next Next Next Next Current Current Current Current Current Current CE H L L L L L L L X X H H X H X X H H X H CE2 X X L X L H H H X X X X X X X X X X X X CE2 X H X H X L L L X X X X X X X X X X X X ADSP ADSC X L L X L X H L H L L X H L H L H H H H X H X H H H X H H H H H X H X H H H X H ADV WRITE X X X X X X X X X X X X X Read X Write L Read L Read L Read L Read L Write L Write H Read H Read H Read H Read H Write H Write
ISSI
OE X X X X X X X X L H L H X X L H L H X X DQ High-Z High-Z High-Z High-Z High-Z Q Q D Q High-Z Q High-Z D D Q High-Z Q High-Z D D
(R)
PARTIAL TRUTH TABLE
Function Read Read Write Byte 1 Write All Bytes Write All Bytes GW H H H H L BWE H L L L X BWa X H L L X BWb X H H L X BWc X H H L X BWd X H H L X
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
9
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
INTERLEAVED BURST ADDRESS TABLE (MODE = VCC or No Connect)
External Address A1 A0 00 01 10 11 1st Burst Address A1 A0 01 00 11 10 2nd Burst Address A1 A0 10 11 00 01 3rd Burst Address A1 A0 11 10 01 00
ISSI
(R)
LINEAR BURST ADDRESS TABLE (MODE = GND)
0,0
A1', A0' = 1,1
0,1
1,0
ABSOLUTE MAXIMUM RATINGS(1)
Symbol TBIAS TSTG PD IOUT VIN, VOUT VIN VCC Parameter Temperature Under Bias Storage Temperature Power Dissipation Output Current (per I/O) Voltage Relative to GND for I/O Pins Voltage Relative to GND for for Address and Control Inputs Voltage on Vcc Supply Relatiive to GND Value Unit -40 to +85 C -55 to +150 C 1.6 W 100 mA -0.5 to VCCQ + 0.5 V -0.5 to VCC + 0.5 V -0.5 to 4.6 V
Notes: 1. Stress greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. This device contains circuity to protect the inputs against damage due to high static voltages or electric fields; however, precautions may be taken to avoid application of any voltage higher than maximum rated voltages to this high-impedance circuit. 3. This device contains circuitry that will ensure the output devices are in High-Z at power up.
10
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PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
OPERATING RANGE
Range Commercial Industrial Ambient Temperature 0C to +70C -40C to +85C VCC 3.3V, +10%, -5% 3.3V, +10%, -5% VCCQ 2.375-3.6V 2.375-3.6V
ISSI
(R)
DC ELECTRICAL CHARACTERISTICS(1) (Over Operating Range)
Symbol Parameter VOH VOL VIH VIL ILI ILO Output HIGH Voltage Output LOW Voltage Input HIGH Voltage Input LOW Voltage Input Leakage Current Output Leakage Current Test Conditions IOH = -2.0 mA, VCCQ = 2.5V IOH = -4.0 mA, VCCQ = 3.3V IOL = 2.0 mA, VCCQ = 2.5V IOL = 8.0 mA, VCCQ = 3.3V VCCQ = 2.5V VCCQ = 3.3V VCCQ = 2.5V VCCQ = 3.3V GND VIN VCCQ(2) Com. Ind. Min. 1.7 2.4 -- -- 1.7 2.0 -0.3 -0.3 -2 -5 -2 -5 Max. -- -- 0.7 0.4 VCCQ + 0.3 VCCQ + 0.3 0.7 0.8 2 5 2 5 Unit V V V V V V V V A A
GND VOUT VCCQ, OE = VIH Com. Ind.
POWER SUPPLY CHARACTERISTICS (Over Operating Range)
Symbol Parameter ICC AC Operating Supply Current Test Conditions Device Selected, All Inputs = VIL or VIH OE = VIH, Vcc = Max. Cycle Time tKC min. Device Deselected, VCC = Max., All Inputs = VIH or VIL CLK Cycle Time tKC min. Com. Ind. -166* Max. 400 -- -150 Max. 370 400 -133 Max. 350 380 -100 Max. 300 330 Unit mA mA
ISB
Standby Current
Com. Ind.
110 --
105 110
90 95
80 85
mA mA
*This speed available only in SPD version Notes: 1. The MODE pin has an internal pullup. This pin may be a No Connect, tied to GND, or tied to VCC. 2. The MODE pin should be tied to Vcc or GND. It exhibits 10 A maximum leakage current when tied to - GND + 0.2V or Vcc - 0.2V.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
11
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
CAPACITANCE(1,2)
Symbol CIN COUT Parameter Input Capacitance Input/Output Capacitance Conditions VIN = 0V VOUT = 0V Max. 6 8 Unit pF pF
ISSI
(R)
Notes: 1. Tested initially and after any design or process changes that may affect these parameters. 2. Test conditions: TA = 25C, f = 1 MHz, Vcc = 3.3V.
AC TEST CONDITIONS
Parameter Input Pulse Level Input Rise and Fall Times Input and Output Timing and Reference Level Output Load Unit 0V to 3.0V 1.5 ns 1.5V for 3.3V I/O VCCQ/2V for 2.5V I/O See Figures 1 and 2
AC TEST LOADS
317 /1667 3.3V for 3.3V I/O /2.5V for 2.5v I/O
ZO = 50 Output Buffer
50
OUTPUT 5 pF Including jig and scope 351 /1538
1.5V for 3,3V I/O VCCQ/2V for 2.5V I/O
Figure 1
Figure 2
12
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
READ/WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter fMAX tKC tKH tKL tKQ tKQX
(1)
ISSI
-150 Min. Max. -- 6.7 2.5 2.5 -- 1.5 0 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 150 -- -- -- 3.8 -- -- 3.8 3.8 -- 3.8 -- -- -- -- -- -- -- -- -- -- -133 Min. Max. -- 7.5 2.8 2.8 -- 1.5 0 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 133 -- -- -- 4 -- -- 4 4 -- 4 -- -- -- -- -- -- -- -- -- -- -100 Min. Max. -- 10 3 3 -- 1.5 0 -- -- 0 -- 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 100 -- -- -- 5 -- -- 5 5 -- 5 -- -- -- -- -- -- -- -- -- -- Unit MHz ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
-166* Min. Max. -- 6 2.3 2.3 -- 1.5 0 -- -- 0 -- 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 166 -- -- -- 3.5 -- -- 3.5 3.5 -- 3.2 -- -- -- -- -- -- -- -- -- --
Clock Frequency Cycle Time Clock High Pulse Width Clock Low Pulse Width Clock Access Time Clock High to Output Invalid Clock High to Output Low-Z Output Enable to Output Valid
(1,2)
tKQLZ(1,2) tOEQ tOELZ tAS tSS tWS tCES tAVS tAH tSH tWH tCEH tAVH
tKQHZ(1,2) Clock High to Output High-Z Output Enable to Output Low-Z Address Setup Time Address Status Setup Time Write Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time
tOEHZ(1,2) Output Enable to Output High-Z
*This speed available only in SPD version Note: 1. Guaranteed but not 100% tested. This parameter is periodically sampled. 2. Tested with load in Figure 2.
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
13
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
READ/WRITE CYCLE TIMING
tKC
ISSI
ADSP is blocked by CE inactive
(R)
CLK
tSS tSH tKH tKL
ADSP
tSS tSH
ADSC initiate read
ADSC
tAVS tAVH
Suspend Burst
ADV
tAS tAH
Address
RD1
tWS tWH
RD2
RD3
GW
tWS tWH
BWE
BWx
tCES tCEH
CE Masks ADSP
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
tOEQ tOEHZ
OE
tOELZ tOEQX tKQX
DATAOUT
High-Z
tKQLZ tKQ
1a
2a
2b
2c
2d
3a
tKQHZ
DATAIN
High-Z Pipelined Read Single Read Burst Read Unselected
14
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
WRITE CYCLE SWITCHING CHARACTERISTICS (Over Operating Range)
Symbol Parameter tKC tKH tKL tAS tSS tWS tDS tCES tAVS tAH tSH tDH tWH tCEH tAVH Cycle Time Clock High Pulse Width Clock Low Pulse Width Address Setup Time Address Status Setup Time Write Setup Time Data In Setup Time Chip Enable Setup Time Address Advance Setup Time Address Hold Time Address Status Hold Time Data In Hold Time Write Hold Time Chip Enable Hold Time Address Advance Hold Time -166* Min. Max. 6 2.3 2.3 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -150 Min. Max. 6.7 2.5 2.5 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -133 Min. Max. 7.5 2.8 2.8 1.5 1.5 1.5 1.5 1.5 1.5 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- --
ISSI
-100 Min. Max. 10 3 3 2 2 2 2 2 2 0.5 0.5 0.5 0.5 0.5 0.5 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns
(R)
*This speed available only in SPD version
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
15
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
WRITE CYCLE TIMING
tKC
ISSI
ADSP is blocked by CE inactive
(R)
CLK
tSS tSH tKH tKL
ADSP ADSC initiate Write ADSC ADV must be inactive for ADSP Write tAVS ADV
tAS tAH tAVH
Address
WR1
tWS tWH
WR2
WR3
GW
tWS tWH
BWE
tWS tWH tWS tWH
BWx
tCES tCEH
WR1
WR2 CE Masks ADSP
WR3
CE
tCES tCEH
CE2 and CE2 only sampled with ADSP or ADSC
Unselected with CE2
CE2
tCES tCEH
CE2
OE
DATAOUT
High-Z
tDS tDH
BW4-BW1 only are applied to first cycle of WR2 2a 2b 2c 2d 3a
DATAIN
High-Z
1a
Single Write
Burst Write
Write
Unselected
16
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
SNOOZE MODE ELECTRICAL CHARACTERISTICS
Symbol ISB2 tPDS tPUS tZZI tRZZI Parameter Current during SNOOZE MODE ZZ active to input ignored ZZ inactive to input sampled ZZ active to SNOOZE current ZZ inactive to exit SNOOZE current Conditions ZZ Vih Min. -- -- 2 -- 0 Max. 30 2 -- 2 --
ISSI
Unit mA cycle cycle cycle ns
(R)
SLEEP MODE TIMING
CLK
tPDS ZZ setup cycle tPUS ZZ recovery cycle
ZZ
tZZI
Isupply
ISB2 tRZZI
All Inputs (except ZZ)
Deselect or Read Only
Deselect or Read Only Normal operation cycle
Outputs (Q)
High-Z Don't Care
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
17
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D PART IDENTIFICATION PART IDENTIFICATION
ISSI
(R)
61XPDXXXXXX-XXXXXX
Rating Commercial I - Industrial TQ - TQFP B - PBGA
Package
Speed T - Three chip selects D - Two chip selects Density 25632 - 256K x 32 25636 - 256K x 36 51218 - 512K x 18 D - double-cycle dedelect S - single-cycle deselect SP - 3.3V I/O synchronous pipeline LP - 2.5V I/O synchronous pipeline
166 - 166 MHz 150 - 150 MHz 133 - 133 MHz 5 - 100 MHz
18
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 166 MHz Order Part Number IS61SPD25632T-166TQ IS61SPD25632D-166TQ IS61SPD25632D-166B IS61SPD25632T-150TQ IS61SPD25632D-150TQ IS61SPD25632D-150B IS61SPD25632T-133TQ IS61SPD25632D-133TQ IS61SPD25632D-133B IS61SPD25632T-5TQ IS61SPD25632D-5TQ IS61SPD25632D-5B Package TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA
ISSI
Commercial Range: 0C to +70C
Speed 166 MHz Order Part Number IS61SPD25636T-166TQ IS61SPD25636D-166TQ IS61SPD25636D-166B IS61SPD25636T-150TQ IS61SPD25636D-150TQ IS61SPD25636D-150B IS61SPD25636T-133TQ IS61SPD25636D-133TQ IS61SPD25636D-133B IS61SPD25636T-5TQ IS61SPD25636D-5TQ IS61SPD25636D-5B Package TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA
(R)
150 MHz
150 MHz
133 MHz
133 MHz
100 MHz
100 MHz
Industrial Range: -40C to +85C
Speed 150 MHz 133 MHz 100 MHz Order Part Number IS61SPD25632T-150TQI IS61SPD25632D-150TQI IS61SPD25632T-133TQI IS61SPD25632D-133TQI IS61SPD25632T-5TQI IS61SPD25632D-5TQI Package TQFP TQFP TQFP TQFP TQFP TQFP
Industrial Range: -40C to +85C
Speed 150 MHz 133 MHz 100 MHz Order Part Number IS61SPD25636T-150TQI IS61SPD25636D-150TQI IS61SPD25636T-133TQI IS61SPD25636D-133TQI IS61SPD25636T-5TQI IS61SPD25636D-5TQI Package TQFP TQFP TQFP TQFP TQFP TQFP
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
19
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 166 MHz Order Part Number IS61SPD51218T-166TQ IS61SPD51218D-166TQ IS61SPD51218D-166B IS61SPD51218T-150TQ IS61SPD51218D-150TQ IS61SPD51218D-150B IS61SPD51218T-133TQ IS61SPD51218D-133TQ IS61SPD51218D-133B IS61SPD51218T-5TQ IS61SPD51218D-5TQ IS61SPD51218D-5B Package TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA
ISSI
(R)
150 MHz
133 MHz
100 MHz
Industrial Range: -40C to +85C
Speed 150 MHz 133 MHz 100 MHz Order Part Number IS61SPD51218T-150TQI IS61SPD51218D-150TQI IS61SPD51218T-133TQI IS61SPD51218D-133TQI IS61SPD51218T-5TQI IS61SPD51218D-5TQI Package TQFP TQFP TQFP TQFP TQFP TQFP
20
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 150 MHz Order Part Number IS61LPD25632T-150TQ IS61LPD25632D-150TQ IS61LPD25632D-150B IS61LPD25632T-133TQ IS61LPD25632D-133TQ IS61LPD25632D-133B IS61LPD25632T-5TQ IS61LPD25632D-5TQ IS61LPD25632D-5B Package TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA
ISSI
Commercial Range: 0C to +70C
Speed 150 MHz Order Part Number IS61LPD25636T-150TQ IS61LPD25636D-150TQ IS61LPD25636D-150B IS61LPD25636T-133TQ IS61LPD25636D-133TQ IS61LPD25636D-133B IS61LPD25636T-5TQ IS61LPD25636D-5TQ IS61LPD25636D-5B Package TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA
(R)
133 MHz
133 MHz
100 MHz
100 MHz
Industrial Range: -40C to +85C
Speed 133 MHz 100 MHz Order Part Number IS61LPD25632T-133TQI IS61LPD25632D-133TQI IS61LPD25632T-5TQI IS61LPD25632D-5TQI Package TQFP TQFP TQFP TQFP
Industrial Range: -40C to +85C
Speed 133 MHz 100 MHz Order Part Number IS61LPD25636T-133TQI IS61LPD25636D-133TQI IS61LPD25636T-5TQI IS61LPD25636D-5TQI Package TQFP TQFP TQFP TQFP
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION 04/17/01 Rev. 00A
21
IS61SPD25632T/D IS61LPD25632T/D IS61SPD25636T/D IS61LPD25636T/D IS61SPD51218T/D IS61LPD51218T/D
ORDERING INFORMATION Commercial Range: 0C to +70C
Speed 150 MHz Order Part Number IS61LPD51218T-150TQ IS61LPD51218D-150TQ IS61LPD51218D-150B IS61LPD51218T-133TQ IS61LPD51218D-133TQ IS61LPD51218D-133B IS61LPD51218T-5TQ IS61LPD51218D-5TQ IS61LPD51218D-5B Package TQFP TQFP PBGA TQFP TQFP PBGA TQFP TQFP PBGA
ISSI
(R)
133 MHz
100 MHz
Industrial Range: -40C to +85C
Speed 133 MHz 100 MHz Order Part Number IS61LPD51218T-133TQI IS61LPD51218D-133TQI IS61LPD51218T-5TQI IS61LPD51218D-5TQI Package TQFP TQFP TQFP TQFP
ISSI
(R)
Integrated Silicon Solution, Inc.
2231 Lawson Lane Santa Clara, CA 95054 Tel: 1-800-379-4774 Fax: (408) 588-0806 E-mail: sales@issi.com www.issi.com
22
Integrated Silicon Solution, Inc. -- 1-800-379-4774
PRELIMINARY INFORMATION Rev. 00A 04/17/01

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